Course on SystemVerilog for ASIC/FPGA Design & Simulation

The Department of Electronic and Telecommunication Engineering at the University of Moratuwa, in collaboration with Synopsys Sri Lanka and Skill Surf, has started an 8-week course on “SystemVerilog for ASIC/FPGA Design & Simulation”. The course is designed to equip participants with the necessary skills and knowledge to contribute to the global innovations chain, particularly in the era of “Smart Everything”.

The course covers digital design with SystemVerilog and emphasizes best practices that match the industry standards. Participants are given hands-on experience on SystemVerilog and Synopsys tools, thanks to our partnership with Synopsys. We are grateful for this partnership and the opportunity it provides for participants to gain practical experience with industry-standard tools.

The need for skilled engineers in digital design has grown with the development of the Internet of Things (IoT) and other technological advancements. By participating in this course, individuals can develop their skills and contribute to meeting this growing need. The course is open to beginners and those who aspire to become design and verification engineers.

Registrations for the course closed on 5th February 2023, and the opening session was held on 12th February 2023. The program is progressing well, with a diverse group of participants from universities and industry in Sri Lanka and overseas.

The course provides a valuable opportunity for participants to gain knowledge and skills in digital design with SystemVerilog, and to gain practical experience with Synopsys tools, which are widely used in the industry. We are proud to offer this course and to partner with Synopsys Sri Lanka and Skill Surf to provide a valuable learning experience for participants.