Department Publications

Traditional boundary scan chain implementations are typically linear and fixed in length for specific designs, with continuous testing being their primary application. However, these chains also play a critical role in continuous monitoring, where the standard architecture, originally intended for testing, is not fully optimized. In particular, input ports that do not contribute to data capture are still included in the scan path, resulting in unnecessary scanning and reduced efficiency. Since the scan chain is linear, the Test Access Port controller must sequentially access all cells, including irrelevant ones, leading to slower monitoring speeds. In this research, we propose a novel boundary scan architecture that enhances both continuous testing and monitoring by focusing only on relevant input ports for test pattern insertion and output ports for response capture. This targeted approach significantly improves monitoring …

In this paper, we propose a method for duplicating digital circuits using neural networks (NNs). Our approach involves training a common neural network model on the inputs and outputs of existing digital circuits, creating a digital twin. This digital twin can be used to predict the outputs of a digital I'C, only using its inputs and this has been verified using counter circuits, and shift register circuits. Moreover, we have successfully validated the functionality duplication of digital logic in a robotic arm equipped with servo motors, further validating the utility of our approach.

With the advancement of technology, the digital Integrated Circuit (IC) design process has become more complex and denser. Hence, the IC testing procedure requires high-end test equipment to validate the accuracy and reliability of the manufactured components. Testers with such capabilities usually cost millions of dollars. In this paper, the authors have presented a low-cost hardware and software solution for digital IC testing. Digital ICs which operate under the 100MHz range can be easily tested in the digital domain with the FPGA-based test environment. The presented design comprises of a scalable architecture with a set of clock synchronized Altera DE0-Nano Field Programmable Gate Arrays (FPGAs) which handles the digital testing of Device Under Test (DUT) at a low cost. The digital test patterns are generated inside a computer, which transfers them to the FPGA environment and feeds them to DUT. The …

This paper identifies the challenges involved in designing the 100 Gigabit per second (Gbps) Ethernet Physical Coding Sublayer (PCS) Semiconductor Intellectual property (IP) compliant with IEEE 802.3 standard. Challenges are discussed under the two topics, implementation challenges and verification challenges. Furthermore, our solutions to identified challenges are presented in the paper.

This paper analyses the receiver of 40GBASE PCS Sub layer specified by IEEE 802.3ba CSMA/CD standards. Based on the analysis, possible optimization parameters for the receiver FIFO are identified. Proper functionality of the proposed design is verified with simulation results. The optimization of receiver FIFO design may lead to reduce the gate count, area and power consumption in ASIC design.

This paper presents an implementation technique for the 40Gbps Ethernet Physical Coding Sublayer (PCS). The functionality of the 40Gbps Ethernet PCS is specified in the IEEE 802.3ba standard's clause 82. The paper also presents a scheme of verification of this implementation using an FPGA setup.

The design and implementation of a low cost bell and light protection system for a railway level crossing is described. This is directly targeted to cater for the un protected level crossings in Sri Lanka. The design is entirely hardware oriented. It detects the presence of a train on the rail track to activate a set of red lights and a bell to warn the road users. To enhance the reli ability of the system, the electrical continuity of the rail track is also monitored.

The concept of vision information has become a key feature in modern vehicular traffic control and Intelligent Vehicle Highway Systems (IVHS)[1]. Vehicle detection by video cameras is one of the most promising new technologies used in implementing advanced traffic control and management systems [2].

In present day workstations, high quality visualization and interaction facilities are becoming essential features. Recognizing this, system designers paid special attention to the image generation pipeline in order to improve both image quality and interaction behaviour. By improving the image generation pipeline, the frame buffer access bottleneck became more and more apparent. To overcome this problem, all sorts of partitioning

The concept of vision information has become a key feature in modern vehicular traffic control and Intelligent Vehicle Highway Systems (IVHS)[1]. Vehicle detection by video cameras is one of the most promising new technologies used in implementing advanced traffic control and management systems [2]. The CCTV Image Grabber discussed in this paper is a low cost design which can capture, store and transmit video information to a remote computer for visual site inspection and extraction of vehicular traffic parameters for adaptive control of road traffic.

In an integrated plant environment, it is not feasible to replace an existing field device with a different model unless the protocols are properly matched. The system complexity is a deterrent to a software modification in order to tackle the problem. A microcontroller based interface card would be an elegant solution. This card takes information from the new device and manipulates it dynamically so that the central controller can understand and vice versa. Due to the new features of microcontrollers, design and development of such cards are not intricate.

The design and implementation of a low cost solid-state lamp driver and failure detector (LD/FD) for incandescent lamps is described. The design is directly targeted for the signal lamp heads in highway traffic signal systems. This is entirely hardware oriented and can be used to replace the relay systems currently used without doing any modification to control signals. The incorporated lamp failure detection circuitry enhances the features of the design by activating a feed back signal to indicate lamp failures. This feature enables us to develop an automated maintenance scheme in a centralized traffic control system such as the emerging Advanced Traffic Control System (ATCS).