Department Publications

The optimal selection of approximate computing units towards low-complexity FPGA-based hardware architectures for approximate discrete cosine transform (ADCT) and approximate discrete Fourier transform (ADFT) are explored. The proposed methodology employs an existing library of FPGA based approximate adders to select Pareto-optimal 1 approximate adders for cascaded signal flow architectures found in ADCT and ADFT operations. Benefits are presented with examples from 8-point ADCT based image compression and 16-point ADFT based digital multi-beamforming applications. Examples demonstrate a nearly 25% LUT reduction in FPGA utilization compared to error-free computing, with a corresponding degradation of nearly 1 dB in terms of PSNR in image compression and 0.3 dB loss in SNR improvement in beamforming.

The 6-24 GHz upper midband - FR3 range - is the next generation spectrum for mobile wireless applications. Traditionally allocated for defense and scientific use cases, the possible adoption of FR3 frequencies for commercial applications opens the possibility for severe interference between different commercial and scientific/defense systems. We demonstrate lowcomplexity adaptive array processing in the FR3 range using realtime implementation in the 10.7-10.8 GHz band, with 100 MHz of bandwidth using Xilinx Virtex-6 Sx475T FPGA technology. The demonstration supports a uniform linear array with 8 Vivaldi antennas (6-24 GHz) and can provide up to 6 nulls in the aperture pattern in addition to the desired RF beam. The FPGA back-end utilizes sampling at 200 MS/s and exploits digital signal processing to furnish up to 100 MHz of bandwidth at IF.

The combined use of algorithms for approximate discrete cosine transform (DCT) with approximate computing is examined toward area-efficient field programmable gate array (FPGA) hardware architectures. The performance of previously reported, multiplierless approximate DCT transforms are explored in the presence of non-exact hardware adders which provide better utilisation of FPGA resources in terms of look-up-tables (LUTs). In the context of 2D image compression, provided examples are demonstrating a 20% LUT reduction in FPGA utilization compared to accurate adders, with a corresponding image quality degradation of 0.6 dB in terms of PSNR. The potential benefit of such area-efficient FPGA hardware designs is explored on 3D (video compression), 4D (static light field compression), and 5D (light field video compression) cases where significant FPGA resource savings are obtained at the cost of …

Real-time sensing and perception of the radio spectrum based on artificial intelligence (AI) is crucial for emerging intelligent wireless and electronic warfare systems. However, sensing can be greatly impacted by harmful radio frequency interference (RFI). Emerging drone warfare allows many RFI sources/jammers to be distributed across a wide field-of-view which necessitates real-time measurement, adaptation and aperture nulling to remove the RFI before AI-based sensing and perception of sources of interest can occur. This work explores algorithmic innovations that improve the computational complexity of classical Howells-Applebaum adaptive nulling algorithm to enable fast, real-time adaptive operation at significantly lower arithmetic complexity. Design examples for AI-enabled sensing and perception across a 32-element antenna receiver with 32 independent channels and a Xilinx Virtex-6 Sx475 FPGA …

The radio spectrum is a scarce and extremely valuable resource that demands careful real-time monitoring and dynamic resource allocation. Dynamic spectrum access (DSA) is a new paradigm for managing the radio spectrum, which requires AI/ML-driven algorithms for optimum performance under rapidly changing channel conditions and possible cyber-attacks in the electromagnetic domain. Fast sensing across multiple directions using array processors, with subsequent AI/ML-based algorithms for the sensing and perception of waveforms that are measured from the environment is critical for providing decision support in DSA. As part of directional and wideband spectrum perception, the ability to finely channelize wideband inputs using efficient Fourier analysis is much needed. However, a fine-grain fast Fourier transform (FFT) across a large number of directions is computationally intensive and leads to a high chip area and power consumption. We address this issue by exploiting the recently proposed approximate discrete Fourier transform (ADFT), which has its own sparse factorization for real-time implementation at a low complexity and power consumption. The ADFT is used to create a wideband multibeam RF digital beamformer and temporal spectrum-based attention unit that monitors 32 discrete directions across 32 sub-bands in real-time using a multiplierless algorithm with low computational complexity. The output of this spectral attention unit is applied as a decision variable to an intelligent receiver that adapts its center frequency and frequency resolution via FFT channelizers that are custom-built for real-time monitoring at high …

The radio spectrum is a scarce and extremely valuable resource that demands careful real-time monitoring and dynamic resource allocation. Dynamic spectrum access (DSA) is a new paradigm for managing the radio spectrum, which requires AI/ML driven algorithms for optimum performance under rapidly changing channel conditions and possible cyber attacks in the electromagnetic domain. Fast sensing across multiple directions using array processors, with subsequent AI/ML based algorithms for sensing and perception of the waveforms that are measured from the environment is critical for providing decision support in DSA. As part of directional and wideband spectrum perception, the ability to finely channelize wideband inputs using efficient Fourier analysis is much needed. However, a fine-grain fast Fourier transform (FFT) across a large number of directions is computationally intensive and leads to high chip area and power consumption. We address this issue by exploiting recently proposed approximate discrete Fourier transforms (ADFT) which has its own sparse factorization for real-time implementation at low complexity and power consumption. The ADFT is used to create a wideband multi-beam RF digital beamformer and temporal spectrum-based attention unit which monitors 32 discrete directions across 32 sub-bands in real-time using a multiplierless algorithm having low computational complexity. The output of this spectral attention unit is applied as a decision variable to an intelligent receiver that adapts its center frequency and frequency resolution via FFT channelizers that are custom-built for real-time monitoring at high …

The real-time adaptive nulling of a digital beamformer is crucial for receiving weak signals in a high RFI or RF denied environment. The Howells-Applebaum and MVDR adaptive beamformers use the Weiner optimum solution to ensure that RFI sources are blanked out in an array processor. In this paper, we create a custom 32-channel fully-digital array operating at 5.7-5.8 GHz, with real-time FPGA processing for both adaptation and subsequent beamforming with RFI suppression. Real-time measurements with up to three RFI sources show correct real-time digital beamforming in the FPGA processor. The developed microwave and digital systems along with hardware accelerated Howells-Applebaum array-null adaptation architecture will be used as a building block to create RF identification, location, spectrum sensing, and wireless communications that are resilient to jammers and RFI sources in the environment.

We propose a minimax design method for multi-dimensional (M-D) interpolated finite-support impulse response (IFIR) filters. As a result of the cascade structure of an MD IFIR filter, the optimization problem of the minimax design is nonconvex. In order to solve this nonconvex optimization problem, we employ a convex-concave procedure, where each iteration solves a convex constrained optimization problem. We present experimental results to confirm the effectiveness and the superior performance of the proposed method compared to previously proposed minimax designs of M-D IFIR filters. Furthermore, we present an implementation of M-D IFIR filter on the Xilinx Kintex UltraScale KCU105 field-programmable gate array, where a quantization error of −60.59 dB is achieved with the coefficient word length of 24 bits.

Chromatic derivatives (CDs) and associated chromatic approximations (CAs) provide a numerically robust and powerful framework for digital processing of continuous-time/space signals, using not only the discrete signal amplitudes, but also higher order derivatives. Acquisition of CDs has so far been limited to software implementations. This paper presents field-programmable gate array (FPGA)-based digital hardware architectures suitable for the real-time acquisition of CDs, thus enabling CDs to be used for practical signal processing algorithm development in embedded systems. With 24 bits of fixed-point precision, the proposed hardware architectures provide approximate 116 dB accuracy in the frequency responses of FIR filters capturing the CDs, and 76.85 dB and 75.09 dB accuracy in signal reconstruction with synthetic and real audio signals using CDs up to order 28 degrees. The designs have been …

The use of approximate transforms in conjunction with approximate adder hardware is explored towards implementing low-complexity multi-beam antenna arrays. The use of approximate adders is motivated by the efficient look up table (LUT) usage on field programmable gate arrays (FPGA) resulting in better area and time complexities on hardware. 8-beam and 16-beam hardware architectures for multi-beamforming are designed using previously reported 8-point and 16-point spatial approximate-DFT (ADFT) algorithms, respectively, albeit with approximate adders. Designs have been implemented on Xilinx Kintex UltraScale KCU105 FPGA device verifying 31.5% reduction in (FPGA) LUT count and 58.08% improvement in critical path delay with a maximum beam error of 0.6 degrees and maximum peak side lobe level deviation 0.21 dB for the 8-beam case, when compared to ADFT with accurate adders with the …

Light fields (LFs) and light field videos (LFVs) capture both angular and spatial variation of light rays emanating from scenes. This richness of information leads to novel applications such as post-capture refocusing, depth estimation and depth-velocity filtering which are not possible with images and videos. These capabilities come, however, with a significant increase in data to be processed. In order to fully exploit opportunities provided by LFs and LFVs, low-complexity signal processing algorithms that process LF and LFV data in real-time are required. In this brief, we survey such state-of-the-art algorithms, in particular for depth filtering, refocusing and denoising of LFs and depth-velcoty filtering for LFVs, and future directions for these real-time LF an LFV processing algorithms.

With the advancement of technology, the digital Integrated Circuit (IC) design process has become more complex and denser. Hence, the IC testing procedure requires high-end test equipment to validate the accuracy and reliability of the manufactured components. Testers with such capabilities usually cost millions of dollars. In this paper, the authors have presented a low-cost hardware and software solution for digital IC testing. Digital ICs which operate under the 100MHz range can be easily tested in the digital domain with the FPGA-based test environment. The presented design comprises of a scalable architecture with a set of clock synchronized Altera DE0-Nano Field Programmable Gate Arrays (FPGAs) which handles the digital testing of Device Under Test (DUT) at a low cost. The digital test patterns are generated inside a computer, which transfers them to the FPGA environment and feeds them to DUT. The …

In four-dimensional (4-D) light field (LF) processing, 4-D linear shift-invariant filters having hyperplanar passbands are used for depth-based scene enhancement. In this paper, two low-sensitivity and low-complexity field programmable gate array (FPGA)-based digital hardware architectures for 4-D hyperplanar filters are proposed for on-chip real-time processing of LFs. Both 4-D filters are designed exploiting resonant properties of multi-dimensional passive prototype networks, and are realized as wave digital filters (WDFs). The two 4-D WDF realizations are implemented as raster-scanned processing architectures on a Xilinx Virtex 6 Sx35 FPGA with a real-time clock speed of up to 33 MHz. This corresponds to a real-time throughout of 16.8 LFs/s for an LF of size .

Low-complexity signal processing algorithms and reconfigurable digital hardware architectures are proposed for multi-depth filtering and occlusion suppression in 4-D light fields (LFs). The proposed multi-depth-pass (MDP) and multi-depth-reject (MDR) 4-D filters allow simultaneous enhancement of planar objects at multiple desired depths and attenuation of planar objects at multiple undesired depths, thereby achieving electronically tunable multi-depth focusing. Partial-separability and recursive nature of the proposed MDP and MDR transfer functions ensure ultra-low hardware complexity suitable for real-time processing of large volume of input samples encountered in 4-D LFs. Filter synthesis details and examples with synthetic and real LFs of size 15  ×  15 × 434  ×  625 are presented. A generic framework encapsulating a multitude of possible digital hardware realizations is described, employing J …

This paper describes a technique for de-embedding electromagnetic mutual coupling effects between nearest neighbors of a ULA receiver. Measured S-parameters across a range of frequencies of interest are used in a closed-form mathematical model that relates measured S-parameters, measured LNA reflection coefficients, and transmission line parameters to digital beamformer design equations, such that the beam shape distortions arising from mutual coupling can be compensated in the DSP algorithm. A 5.8 GHz 32-element receiver array with custom receivers and 32-channel Xilinx Virtex-6 Sx35 FPGA based DSP system implementing a real-time complex-valued Frost beamformer operating at IF is proposed to show the benefits of de-embedding mutual coupling for far-field side-lobe suppression. The worst-case side-lobe level is reduced by 11.2 dB, and the average side-lobe level is reduced by 5.2 dB, for …

A low-complexity codec and a hardware architecture are proposed for achieving real-time compression of four-dimensional (4-D) light field (LF) signals captured from camera/lenslet arrays. The proposed system employs the 4-D extension of the two-dimensional (2-D) 8×8 approximate discrete cosine transform (ADCT) that has recently appeared in the literature. Motivated by the partial separability of the multidimensional spectrum of LFs, the proposed 4-D ADCT is obtained by cascading 2-D inter-view and 2-D intra-view transform stages. Software simulations are provided to confirm the performance of the 4-D ADCT based compression and comparisons are made with respect to 2-D inter-view only and 2-D intra-view only ADCT-based compression. Proposed digital architectures are validated using stepped hardware co-simulation on a Xilinx Virtex-7 VC-707 FPGA platform verifying 597 MHz maximum possible …

This paper presents the design, implementation, and the experimental verifications of a 2.4-GHz multibeam array receiver based on two-dimensional (2-D) spatially bandpass (SBP) digital plane wave (PW) filters. The digital array receiver consists of 2.4-GHz 16-element uniform linear array, and quadrature sampling is employed to process the broadband PWs at the baseband. Both 2-D finite impulse response (FIR) and infinite impulse response (IIR) digital filters having multiple trapezoidal-shaped passbands are employed as the 2-D SBP digital PW filters. Both 2-D FIR and IIR trapezoidal filters are implemented on a Xilinx Virtex 6 sx475t field programmable gate array chip that comes with the reconfigurable open architecture computing hardware version-2 (ROACH-2) platform. The 16 in-phase and quadrature-phase downconverted signals are sampled using the ROACH-2 platform and are processed using the …

In Electroencephalography (EEG) classifiers, processing of EEG signals consists of extracting features from EEG signal and then processing those features to classify the signals. As of today, in most EEG processing systems, the classification part is done on software platform even though the feature extraction is done on hardware. Hence this require an operating system which limits the development of portable medical devices. This paper presents the design and implementation of feature classification in EEG signal processing system on Field Programmable Gate Array (FPGA) hardware platform. The classification is done with two-class Linear Discriminant Analysis (LDA), based on the features extracted using Discrete Wavelet Transform (DWT), for EEG signals obtained through PhysioNet website. The final design has minimum resource utilization, hence is able to implement on Basys 3 Artix-7 FPGA Board …

Due to the increasing heterogeneity in network user requirements, dynamically varying day to day network traffic patterns and delay in-network service deployment, there is a huge demand for scalability and flexibility in modern networking infrastructure, which in return has paved way for the introduction of Software Defined Networking (SDN) in core networks. In this paper, we present an FPGA-based switch that is fully compliant with OpenFlow; the pioneering protocol for southbound interface of SDN. The switch architecture is completely implemented on hardware. The design consists of an OpenFlow Southbound agent which can process OpenFlow packets at a rate of 10Gbps. The proposed architecture speed scales up to 400Gbps while it consumes only 60% of resources on a Xilinx Virtex-7 featuring XC7VX485T FPGA.

SMTPE ST 2110 is a professional video over IP standard which enables uncompressed video to be transported as separate video, audio and ancillary data streams, allowing true flexibility in media workflows. Uncompressed video transmission allows professional video environments to achieve high quality video distribution while meeting strict latency requirements. Although this standard can be implemented on software, hardware solutions can achieve superior performance, lower latency and lower power consumption while efficiently handling jitter and packet bursts. This paper presents an FPGA based hardware implementation of a SMPTE ST 2110 compliant end to end solution supporting uncompressed video resolutions of up to 4K at 30fps. Due to its scalability, the architecture can be easily extended to support higher video resolutions and/or multiple video streams. Additionally, the interface modularity of the …

A real-time directional sensing system is proposed for 2.4 GHz ISM band by exploiting the concept of spatiotemporal spectral white spaces. The proposed system consists of a 16-element patch antenna array, an FFT-based multi-beam beamformer and an energy detector. Our system operates at the baseband with quadrature sampling. Furthermore, digital architectures for two energy detectors that employ integrate-and-dump circuits are presented. With the multi-beam beamformer, the first energy detector can be employed to directional sensing and the second can be employed for both directional and spectral sensing of radio frequency sources. The multi-beam beamformer having 16 beams and the energy detectors are implemented on a ROACH-2 based FPGA system with a 160 MHz clock. With an 8-point temporal FFT, the second energy detector provides approximately 20 MHz bandwidth per temporal FFTbin …

Quad High Definition (QHD/4K) Virtual Reality (VR) Headsets with High Dynamic Range (HDR) technology will provide a superior experience to users. Wireless VR headsets are attractive as it offers freedom on mobility and higher user comfort. Cloud and workstations are capable of rendering 4K HDR scenes in real-time with ease. The efficient transmission of these scenes through wireless network requires the use of compression techniques. Decoding 4K HDR frames at VR devices in real-time is a challenge. Given the power and memory efficiency of the hardware decoders, in this paper we propose JPEG-XT Profile C based hardware architecture to decode 4K HDR frames in real-time. We employ novel methods for merged base and residual layer decoding pipelines, design of probability-based hybrid Huffman lookup table architecture and sparsity aware inverse zig-zag processing. Our decoder is implemented …

In recent years, Convolution Neural Network (CNN) gained great success in many applications, especially in computer vision. Now adapting CNN inference on edge devices has become an active research area in embedded vision and hot topic in Edge AI. The primary design hurdles for implementing CNN inference on embedded systems are limited computational resource, memory resource, and power budget. This study presents a novel architecture for SqueezeNet [1] like CNN models, which can be extended to support any CNN model as well. We address two approaches to mitigate resource constraints. First, we use a custom floating point(12 bit for computation and 8bit for storing). Second is slicing the model into a repetitive block called computation blocks. Computation block can be configured dynamically by the host processor to operate in a different mode. We have implemented SqueezeNet v1.1 for …

The design and hardware implementation of a low-complexity signal processing algorithm is proposed for real-time depth-velocity filtering in 5-D light field videos (LFVs). The proposed design is based on a stable 5-D infinite impulse response digital filter having three cascaded sections, each synthesized using the concept of multidimensional passive network resonance. A novel semi-systolic hardware implementation is proposed. Each section of the filter is implemented and tested on a Xilinx Virtex-7 FPGA platform using MATLAB-based hardware co-simulation with both synthetic and real LFV signals. A real-time processing throughput of 467 LFV frames/s is implied with each section of the filter operating at 204, 164, and 115 MHz for input LFV frames of size 9 × 9 × 220 × 360.