Department Publications

Traditional boundary scan chain implementations are typically linear and fixed in length for specific designs, with continuous testing being their primary application. However, these chains also play a critical role in continuous monitoring, where the standard architecture, originally intended for testing, is not fully optimized. In particular, input ports that do not contribute to data capture are still included in the scan path, resulting in unnecessary scanning and reduced efficiency. Since the scan chain is linear, the Test Access Port controller must sequentially access all cells, including irrelevant ones, leading to slower monitoring speeds. In this research, we propose a novel boundary scan architecture that enhances both continuous testing and monitoring by focusing only on relevant input ports for test pattern insertion and output ports for response capture. This targeted approach significantly improves monitoring …

The escalating cost of VLSI packaging, driven by the proliferation of input and output pins and the growing design complexity, necessitates cost-effective solutions. This research paper explores a method to mitigate these costs by leveraging SerDes (Serializer/Deserializer) technology. We aim to reduce the number of I/O pins within internal chips that lack external signal requirements by employing open-source SerDes. We propose an integrated approach to incorporate SerDes into VLSI designs and validate its effectiveness through existing design cases.

Deep neural networks (DNNs) have been successfully employed in a multitude of applications with remarkable performance. As such performance is achieved at a significant computational cost, several embedded applications demand fast and efficient hardware accelerators for DNNs. Previously proposed application specific integrated circuit (ASIC) architectures strive to utilize arrays of hundreds of processing elements (PEs) and reduce power-hungry DRAM accesses using multiple dataflows requiring complex PE architectures. These consume significant area and reduce the maximum clock frequency. This paper introduces the Kraken architecture, which optimally processes the convolutional layers, fully-connected layers, and matrix products of any DNN through a hardware-friendly uniform dataflow. This enables maximal data reuse of weights, inputs, and outputs, with a bare-bones PE design and on-the-fly dynamic reconfiguration. Kraken, implemented in 65-nm CMOS technology at 400 MHz, packs 672 PEs in 7.3 mm2, with a peak performance of 537.6 Gops. Kraken processes the convolutional layers of AlexNet, VGG-16, and ResNet-50 at 336.6, 17.5, and 64.2 frames/s, respectively, hence outperforming the state-of-the-art ASIC architectures in terms of overall performance efficiency, DRAM accesses, arithmetic intensity, and throughput, with 5.8x more Gops/mm2 and 1.6x more Gops/W.

As silicon technology is scaling down, leakage power dissipation has become more significant among the all power dissipation mechanisms of complementary metal oxide semiconductor (CMOS) circuits. Minimum leakage vector (MLV) is a standby leakage power reduction technique for the combinational logic circuits. Though power gating is an excellent leakage power reduction technique compared to MLV standalone power gating technique has some inherent drawbacks like higher wake up time and circuit state loss. In this paper we combine MLV and power gating to achieve more leakage power reduction compared to MLV while mitigating the mentioned drawbacks of full circuit power gating. Instead of full circuit power gating, we developed a simple algorithm which runs in linear time to identify the gates with higher leakage power dissipation around which power gating can be carried out once combination …

This paper presents a novel low-complexity VLSI architecture for an EEG Feature Extraction Platform for wearable health monitoring systems. It integrates a processing core unit, preprocessing FIR filter block and an FFT accelerator. The platform supports 8 scalp EEG channels and it can be scaled up to 16 or 32 EEG channels. In this paper, we analyze several architectural optimizations for hardware implementation of features such as Power Spectral Density, Discrete Wavelet Transform, Autoregression etc. The proposed architecture is easily scalable to new feature extractors. An FFT accelerator is proposed to improve the flexibility of the platform. We provide a comparison with software models for each feature extractor and also validate the platform by implementing a seizure detection algorithm on CHB-MIT Scalp EEG database with an accuracy of over 95%.

Screen content coding (SCC) extension to High Efficiency Video Coding (HEVC) offers substantial compression efficiency over the existing HEVC standard for computer generated content. However, this gain in compression efficiency is achieved at the expense of further computational complexity with several resource hungry coding tools. Hence, extension of SCC to HEVC hardware encoders can be challenging. This paper presents resource efficient hardware designs for two key SCC tools, Intra Block Copy and Palette Coding. Moreover, a new hash search approach is proposed for Intra Block Copy, while a hardware friendly palette indices coding scheme is suggested for Palette Coding. These designs are targeted to achieve the throughput necessary for an 1080p 30 frames/s encoder, and incurs coding loss of 11.4% and 5.1% respectively in all intra configurations. The designs are synthesized for a Virtex-7 …

This paper identifies the challenges involved in designing the 100 Gigabit per second (Gbps) Ethernet Physical Coding Sublayer (PCS) Semiconductor Intellectual property (IP) compliant with IEEE 802.3 standard. Challenges are discussed under the two topics, implementation challenges and verification challenges. Furthermore, our solutions to identified challenges are presented in the paper.

This paper analyses the receiver of 40GBASE PCS Sub layer specified by IEEE 802.3ba CSMA/CD standards. Based on the analysis, possible optimization parameters for the receiver FIFO are identified. Proper functionality of the proposed design is verified with simulation results. The optimization of receiver FIFO design may lead to reduce the gate count, area and power consumption in ASIC design.

This paper analyses the FIFO design for the receiver of 10GBase-X PCS sublayers specified by IEEE 802.3 CSMA/CD Standards. The proposed FIFO design will save the gate count, power and the silicon area in ASIC design considerably.

The authors report a VLSI design of an advanced systolic array graphics (SAG) engine built from pipelined functional units which can generate realistic images interactively for high-resolution displays. They introduce a structured frame store system as an environment for the advanced SAG engine and present the principles and architecture of the advanced SAG engine. They introduce pipelined functional units into this SAG engine to meet the performance requirements. This is done by a formal approach where the original systolic array is represented at bit level by a finite, vertex-weighted, edge-weighted, directed graph. Two architectures built from pipelined functional units are described. A prototype containing nine processing elements was fabricated in a 1.6- mu m CMOS technology.<>

A Token- Based Arbitration Mechanism for Inter-Systolic-Array Communication - University of Twente Research Information Skip to main navigation Skip to search Skip to main content University of Twente Research Information Home University of Twente Research Information Logo Home Profiles Research units Projects Research output Datasets Activities Prizes Press/Media Search by expertise, name or affiliation A Token- Based Arbitration Mechanism for Inter-Systolic-Array Communication F. El hadidy, JAKS Jayasinghe, OE Herrmann Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review Overview Original language Undefined Title of host publication Proceedings of the International Conference on Microelectronics ICM'91 Place of Publication Cairo, Egypt Pages 271-275 Number of pages 0 Publication status Published - 21 Dec 1991 Keywords …

Improvement of the interaction speed of raster graphics systems is an important topic in computer graphics research. A two-level pipelined systolic array graphics engine will be described, which can improve the interaction speed and image quality for high resolution displays.

Relaxed Multi-rate Systolic Array Graphics Engine for High Resotution Real-time Computer Graphics - University of Twente Research Information Skip to main navigation Skip to search Skip to main content University of Twente Research Information Home University of Twente Research Information Logo Home Profiles Research units Projects Research output Datasets Activities Prizes Press/Media Search by expertise, name or affiliation Relaxed Multi-rate Systolic Array Graphics Engine for High Resotution Real-time Computer Graphics JAKS Jayasinghe, OE Herrmann Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review Overview Original language Undefined Title of host publication Eurographics '90 / CE Vendoni and DA Duce (Editors) Place of Publication Amsterdam Pages - Number of pages 0 Publication status Published - 1 Sept 1990 Keywords …

Two-level pipelined relaxed multi-rate systolic array graphics engine - University of Twente Research Information Skip to main navigation Skip to search Skip to main content University of Twente Research Information Home University of Twente Research Information Logo Home Profiles Research units Projects Research output Datasets Activities Prizes Press/Media Search by expertise, name or affiliation Two-level pipelined relaxed multi-rate systolic array graphics engine JAKS Jayasinghe, OE Herrmann Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review Overview Original language Undefined Title of host publication Digest of technical papers vol. XXI Societey for Information display Pages 395-398 Number of pages 4 Publication status Published - 1 Sept 1990 Keywords METIS-113084 Cite this APA Author BIBTEX Harvard Standard RIS …