Department Publications

DART: An Array Processor Based Design Tool for Real-time Systems - University of Twente Research Information Skip to main navigation Skip to search Skip to main content University of Twente Research Information Home University of Twente Research Information Logo Home Profiles Research units Projects Research output Datasets Activities Prizes Press/Media Search by expertise, name or affiliation DART: An Array Processor Based Design Tool for Real-time Systems F. El hadidy, JAKS Jayasinghe Research output: Book/Report › Report › Professional Overview Original language English Place of Publication Enschede Publisher University of Twente Publication status Published - 1 Sept 1991 Keywords METIS-118034 Cite this APA Author BIBTEX Harvard Standard RIS Vancouver Powered by Pure, Scopus & Elsevier Fingerprint Engine™ All content on this site: Copyright © 2025 University of Twente …

In present day workstations, high quality visualization and interaction facilities are becoming essential features. Recognizing this, system designers paid special attention to the image generation pipeline in order to improve both image quality and interaction behaviour. By improving the image generation pipeline, the frame buffer access bottleneck became more and more apparent. To overcome this problem, all sorts of partitioning

Improvement of the interaction speed of raster graphics systems is an important topic in computer graphics research. A two-level pipelined systolic array graphics engine will be described, which can improve the interaction speed and image quality for high resolution displays.

Relaxed Multi-rate Systolic Array Graphics Engine for High Resotution Real-time Computer Graphics - University of Twente Research Information Skip to main navigation Skip to search Skip to main content University of Twente Research Information Home University of Twente Research Information Logo Home Profiles Research units Projects Research output Datasets Activities Prizes Press/Media Search by expertise, name or affiliation Relaxed Multi-rate Systolic Array Graphics Engine for High Resotution Real-time Computer Graphics JAKS Jayasinghe, OE Herrmann Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review Overview Original language Undefined Title of host publication Eurographics '90 / CE Vendoni and DA Duce (Editors) Place of Publication Amsterdam Pages - Number of pages 0 Publication status Published - 1 Sept 1990 Keywords …

Two-level pipelined relaxed multi-rate systolic array graphics engine - University of Twente Research Information Skip to main navigation Skip to search Skip to main content University of Twente Research Information Home University of Twente Research Information Logo Home Profiles Research units Projects Research output Datasets Activities Prizes Press/Media Search by expertise, name or affiliation Two-level pipelined relaxed multi-rate systolic array graphics engine JAKS Jayasinghe, OE Herrmann Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review Overview Original language Undefined Title of host publication Digest of technical papers vol. XXI Societey for Information display Pages 395-398 Number of pages 4 Publication status Published - 1 Sept 1990 Keywords METIS-113084 Cite this APA Author BIBTEX Harvard Standard RIS …

The material in this book documents the presented papers, the discussions and additional contributions triggered by the EUROGRAPHICS workshop on Graphics Hardware held at the annual conference EG'87 in Amsterdam. The first part considers Algorithmic Aspects of graphics systems realisation. It is worthwhile to note that besides" classical" topics like Hidden-line Elimination or Ray-Tracing, new results of computional geometry are presented in a hardware-oriented context. The second part on Subsystems describes hardware solutions for special tasks in the computer image generation pipeline, eg fast coordinate transformation and perspective projection. The last part addresses System Architecture. It demonstrates by rather different examples the wide range of possible and feasible solutions to build graphics hardware. Unlike the situation in graphics software where a common understanding and an accepted concept has been formed by the standardization process, many architectural options are still to be exploited and evaluated. Especially the interaction between VLSI opportunities, newly developed algorithms, and the increasing diversity of applications encourage again and again innovative solutions and keep graphics hardware a lively working area.