Department Publications

This paper presents the implementation of a two-dimensional (2-D) finite-impulse-response (FIR) trapezoidal filter based beamforming array receiver. A 2.4 GHz 16-element receive-mode IQ array is designed and used for physically measuring the beam patterns corresponding to 2-D FIR trapezoidal filters. The 16-element beamformer is implemented using the reconfigurable open architecture computing hardware version-2 (ROACH-2) field programmable gate array (FPGA) platform to perform analog to digital conversion and digital signal processing. The 2-D FIR trapezoidal filter is designed as a 16-spatial input 32-tap filter and is implemented targeting the ROACH-2’s Xilinx Virtex 6 (sx475t) FPGA chip as a filter-and-sum architecture. The receiver array is precisely rotated (keeping the transmitter fixed) to digitally measure the received energy by integrating the instantaneous power of the output of the 2-D FIR …

Convolutional Neural Networks (CNNs) are widely used in deep learning applications, e.g. visual systems, robotics etc. However, existing software solutions are not efficient. Therefore, many hardware accelerators have been proposed optimizing performance, power and resource utilization of the implementation. Amongst existing solutions, Field Programmable Gate Array (FPGA) based architecture provides better cost-energy-performance trade-offs as well as scalability and minimizing development time. In this paper, we present a model-independent reconfigurable co-processing architecture to accelerate CNNs. Our architecture consists of parallel Multiply and Accumulate (MAC) units with caching techniques and interconnection networks to exploit maximum data parallelism. In contrast to existing solutions, we introduce limited precision 32 bit Q-format fixed point quantization for arithmetic representations and …

Most of the intrusion detection and prevention systems (NIDS/NIPS) are utilizing signature based matching which makes use of a stored rule base for distinguishing malicious network traffic. Dynamic rule-base updates has become a requirement due to the increasingly large number of new attack types identified every day, while the downtime associated with rule base updates has become a major drawback in hardware based Network Intrusion Prevention Systems. In addition, the NIPS are facing the challenge of expanding their throughput to cope with the ever growing high bandwidth requirement. This paper presents a novel scalable architecture for a NIPS with stateful packet inspection. The implementation is capable of processing Snort signatures and also analyzing packet streams to detect attacks with TCP segment manipulation. The system ensures run-time rule reconfigurability, which eliminates the risk of …

Highly flexible FPAA and FPGA based universal sensor node design targeting researchers is discussed in this paper. The reconfigurable system is capable of supporting up to three low power analog sensors and two digital sensors in parallel. This facilitates dynamic configurability and remote monitoring by connecting the device to the internet. The design can be utilized in development of remote sensing devices to be establish at locations where frequent repairing and maintenance is difficult. Compensability for aging, adjustability to different environments, flexibility are key advantages of this system.

There exists some common bottlenecks among the many available Software Defined Networking (SDN) controllers. Of these, the current analysis uses the Floodlight software controller to identify bottlenecks. The analysis has implemented these bottlenecks in a Field Programmable Gate Array (FPGA) in order to assess its feasibility. Thereafter, a Hybrid SDN controller has been developed. Generally Hybrid SDN refers to a networking approach where traditional networking and SDN protocols are used and operated in the same environment. Hybrid in this paper context refers to a controller which is developed both on software and hardware platforms in order to achieve a higher scalability which is a current issue existing in software controller, and thereby overcoming the identified bottlenecks. The analysis has offloaded computational intensive models to an FPGA and tested for performance. These performance figures have then been compared against the performance figures as of a stand-alone software controller.

Higher compression efficiency in HEVC encoders comes with increased computational complexity, making real time encoding of high resolution videos a challenging task. This challenge can be addressed by software, yet hardware solutions are more appealing due to their superior performance and low power consumption. This paper presents an FPGA based hardware implementation of an all intra HEVC encoder, which can encode 8 bits per sample, 1920×1080 resolution, 30 frames per second raw video, that is viable in real time even at low operating frequencies. A major obstacle to real time encoding in available architectures is the dependency created by reference generation. Moreover, each coding unit (CU) has to be processed in multiple configurations to determine the most efficient split and prediction mode representation, based on the bit stream generated. We propose a new three stage architecture to …

With the popularization of a quad high-definition/4K video being dependent on the availability of real-time High Efficiency Video Coding (HEVC) decoders, hardware implementations have become more appealing due to their superior performance and low power consumption. In this paper, a field-programmable gate array (FPGA)-based hardware implementation of a 4K 30 frames/s real-time HEVC decoder is presented. An elastically pipelined decoder architecture is used to absorb variations in processing time and each pipeline stage is optimized to use available FPGA primitives. FPGA-specific challenges in managing critical path delays to achieve a target operating frequency of 150 MHz required many architectural novelties, such as exploitation of the sparsity of transformed coefficient matrix, single-cycle reference pixel processing in intra prediction, and flexible block ordering in deblocking filter/sample …

This paper presents an implementation technique for the 40Gbps Ethernet Physical Coding Sublayer (PCS). The functionality of the 40Gbps Ethernet PCS is specified in the IEEE 802.3ba standard's clause 82. The paper also presents a scheme of verification of this implementation using an FPGA setup.

Brain-computer interfaces (BCIs) require real-time feature extraction for translating input EEG signals recorded from a subject into an output command or decision. Owing to the inherent difficulties in EEG signal processing and neural decoding, many of the feature extraction algorithms are complex and computationally demanding. Presently, software does exist to perform real-time feature extraction and classification of EEG signals. However, the requirement of a personal computer is a major obstacle in bringing these technologies to the home and mobile user affording ease of use. We present the FPGA design and novel architecture of a generalized platform that provides a set of predefined features and preprocessing steps that can be configured by a user for BCI applications. The preprocessing steps include power line noise cancellation and baseline removal while the feature set includes a combination of linear …

Complex Event Processing (CEP) is an emerging field in high performance computing paradigm where real time (low latency) computing capability is expected over big data processing (high throughput). Significant number of software architectures have been developed to improve the throughput while reduce the latency but maintaining of the both aspects reaches the limits of the software platforms. This paper proposes a novel custom hardware accelerator architecture framework for CEP in big data domain. The proposed design improves the throughput performance more than 10 times over the software counterpart while keeping the latency value at less than 100 nano seconds. Same Structured Query Language(SQL) type queries used in reference software architecture were used to improve the flexibility. A query compiler based on the same query language grammar was designed to convert the queries in to …

Multi field packet classification is the enabling function for many novel and emerging network applications. Exponential growth of Internet traffic and classification rule sets demand novel hardware based architectural approaches to packet classification. Even though this is an immensely studied area, packet classification that supports scalability in both line rates and rule sets is scarce. In this paper we present experience gained while implementing a parallel packet classification engine architecture on a popular reconfigurable router platform. The architecture exploits parallelism offered in modern hardware technologies to classify multiple packets simultaneously to increase the throughput. The architecture is also capable of utilizing temporal locality present in internet traffic to increase the throughput. The Architecture was implemented on NetFPGA platform and packet classification was done at full line rate without …

Motion Blur due to the relative motion between the camera and object can seriously degrade image quality. We present an FPGA based motion blur detection and correction algorithm which is implemented on top of a configurable soft-processor based architecture. The system consists of two main modules. The blur detection module identifies the blur length and angle, and the restoration module uses regularized inverse filtering to remove the motion blur. The Processing algorithms are implemented as separate cores on the FPGA fabric where the soft processor core is only used for managing system configuration. The system can achieve a frame rate of 15fps for a 720p HD video stream.

In computer vision crass-correlation is a standard approach for local feature matching in feature tracking applications. For this Normalized cross-correlation (NCC) is implemented on spatial domain, because it does not have a simple and efficient frequency domain expression. Therefore in applications which demand real-time processing, a dedicated hardware implementation of NCC is essential to meet the computational cost in spatial domain. In this paper we present a Field Programmable Gate Array (FPGA) implementation of NCC based on the multi-port memory controller together with Fast Normalize Cross-correlation. Practical experimentation shows that our system can achieve frame rates closer to 100 for a search window size of 100x100 and template size of 15x15, with only using two dual-port memories.

In order to obtain depth perception in computer vision, it is needed to process pairs of stereo images. This process is computationally challenging to be carried out in real-time, because it requires the search for matches between objects in both images. Such process is significantly simplified if the images are rectified. Stereo image rectification involves a matrix transformation which when done in software will not produce real-time results although it is very demanding. Therefore, the video streaming and matrix transformation are not usually implemented in the same system. Our product is a stereo camera pair which produces a rectified real time image output with a resolution of 320×240 at a frame rate of 15FPS and delivers them via a 100-Ethernet interface. We use a Spartan 3E FPGA for real-time processing within which we implement an image rectification algorithm.

Control the data flow between device interfaces, processing blocks and memories in a vision system is complex in hardware implementation. In the research, high-level synthesis tool is used to design, implement and test the vision system within the context of required control, synchronization, and parameterization on a processor based platform. In addition, both HLS tools and HDL were used for the development of the processing cores, and the performance of the two versions were analyzed and compared. The operational structures of benchmarked vision core consist of custom vision coprocessor with efficient memory and bus interfaces. The performance properties such as accuracy, throughput and efficiency are measured and presented. Xilinx XC5VLX110T FPGA, has been used for prototype the hardware platforms. According to results, without any complex optimizations, pipeline length and resource …

Real-time scanned-array direct-form-I hardware implementations of two-dimensional (2D) infinite impulse response (IIR) frequency-planar beam plane-wave (PW) filters have potentially wide applications in the directional enhancement of spatio-temporal broadband PWs based on their directions of arrival (DOAs). The proposed prototypes consist of a microphone sensor array, low-noise-amplifiers (LNAs), multiplexers (MUXs), a programmable gain amplifier (PGA), an analog to digital converter (ADC), a digital to analog converter (DAC), and a field programmable gate array (FPGA) circuit based 2D IIR spatio-temporal beam filter implemented on a single Xilinx Virtex2P xc2vp30-7ff896 FPGA chip. Starting from published 1 st -order designs, novel FPGA architectures for highly-selective 2 nd - and 3 rd -order beam PW filters are proposed, simulated, implemented on FPGA, and verified on-chip.

Real-time image processing demands much more processing power than a conventional processor can deliver. As a result hardware acceleration became necessary to augments processors with application-specific coprocessors. Due to the limited resources on FPGA and nature of some sequential algorithms, it is difficult to depend entirely on slice resources. In this research, we implemented a multiprocessor architecture to support real-time image processing on FPGA. Furthermore, we benchmarked and compared our implemented architectures with their counterparts. The operational structure of multiprocessor architecture consists of on-chip processors implemented in a parallel manner with efficient memory and bus architectures. The performance properties such as accuracy, throughput and efficiency are measured and presented. Multiprocessor systems are effective in software level parallelism on FPGA. Our …

Beamforming, in brief, is a signal processing technique which has potential applications in the areas such as sonar, ultrasound, seismic, microwave imaging, radio astronomy and communications. In this report we are presenting a prototype that filters audio signals of interest, based on their direction of arrival (DOA). The prototype described in this report consists of both hardware and software. A microphone sensor array, low-noise-amplifiers, multiplexer, adjustable gain controller, FPGA development board and speakers constitute the hardware. FPGA processor is embedded with a 2D IIR beam filter. The hardware take the audio inputs, multiplex them, digitize them and finally fed them in to FPGA processor. The digital filter, filters the asynchronously sampled broadband spatio-temporal plane-wave signals based on DOA and yields a processed signal as the output. Further the report describes the synthesis of 2D IIR …

A single-chip FPGA implementation of a vision core is an efficient way to design fast and compact embedded vision systems from the PCB design level. The scope of the research is to design a novel FPGA-based parallel architecture for embedded vision entirely with on-chip FPGA resources. We designed it by utilizing block-RAMs and IO interfaces on the FPGA. As a result, the system is compact, fast and flexible. We evaluated this architecture for several mid-level neighborhood algorithms using Xilinx Virtex-2 Pro (XC2VP30) FPGA. Our algorithm uses a vision core with a 100 MHz system clock which supports image processing on a low-resolution image of 128×128 pixels up to 200 images per second. The results are accurate. We have compared our results with existing FPGA implementations. The performance of the algorithms could be substantially improved by applying sufficient parallelism.

In this paper the design and implementation of a microprocessor for motion control for a Mobile Stereo Camera Platform for Active Vision, is presented. The Stereo Camera Platform has seven degrees of freedom which can simulate neck and eye movements of humans. The microprocessor interprets the instructions given by the user, does the relevant calculations and drives the seven degrees of freedom of the camera platform. The microprocessor was implemented on FPGA using Verilog hardware description language.