Department Publications

The escalating cost of VLSI packaging, driven by the proliferation of input and output pins and the growing design complexity, necessitates cost-effective solutions. This research paper explores a method to mitigate these costs by leveraging SerDes (Serializer/Deserializer) technology. We aim to reduce the number of I/O pins within internal chips that lack external signal requirements by employing open-source SerDes. We propose an integrated approach to incorporate SerDes into VLSI designs and validate its effectiveness through existing design cases.