Minimum leakage vector with sparse power gating–a combinational approach for standby leakage power reduction in CMOS circuits
Abstract
As silicon technology is scaling down, leakage power dissipation has become more significant among the all power dissipation mechanisms of complementary metal oxide semiconductor (CMOS) circuits. Minimum leakage vector (MLV) is a standby leakage power reduction technique for the combinational logic circuits. Though power gating is an excellent leakage power reduction technique compared to MLV standalone power gating technique has some inherent drawbacks like higher wake up time and circuit state loss. In this paper we combine MLV and power gating to achieve more leakage power reduction compared to MLV while mitigating the mentioned drawbacks of full circuit power gating. Instead of full circuit power gating, we developed a simple algorithm which runs in linear time to identify the gates with higher leakage power dissipation around which power gating can be carried out once combination …