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1 publication found

High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension

Rajitha Senanayake, Naduni Damsari Liyanage, Sameera Wijeratne, Sachille Atapattu, Kasun Athukorala, PMK Tharaka, Geethan Karunaratne, RMAU Senarath, Ishanka S Perera, Ashen Ekanayake, Ajith Pasqual

Conference ASAP 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP) , pp. 164-169 · 2017 · Cited by 8

Digital Signal ProcessingVLSI and ASIC DesignHardware Acceleration and Co-design

Abstract

Screen content coding (SCC) extension to High Efficiency Video Coding (HEVC) offers substantial compression efficiency over the existing HEVC standard for computer generated content. However, this gain in compression efficiency is achieved at the expense of further computational complexity with several resource hungry coding tools. Hence, extension of SCC to HEVC hardware encoders can be challenging. This paper presents resource efficient hardware designs for two key SCC tools, Intra Block Copy and Palette Coding. Moreover, a new hash search approach is proposed for Intra Block Copy, while a hardware friendly palette indices coding scheme is suggested for Palette Coding. These designs are targeted to achieve the throughput necessary for an 1080p 30 frames/s encoder, and incurs coding loss of 11.4% and 5.1% respectively in all intra configurations. The designs are synthesized for a Virtex-7 …