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1 publication found

FIFO Design for IEEE 802.3 Standard 10GBase-X PCS and XGXS Sublayers

Subramaniam Thayaparan, Anuradha Nanayakkara

Conference 2013 4th International Conference on Intelligent Systems, Modelling and Simulation , pp. 589-591 · 2013 · Cited by 2

VLSI and ASIC Design

Abstract

This paper analyses the FIFO design for the receiver of 10GBase-X PCS sublayers specified by IEEE 802.3 CSMA/CD Standards. The proposed FIFO design will save the gate count, power and the silicon area in ASIC design considerably.