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4 publications found

Context-aware multipath networks

Dumindu Tissera, Kumara Kahatapitiya, Rukshan Darshana Wijesinghe, Shantha Fernando, Ranga Rodrigo

Preprint arXiv arXiv preprint arXiv:1907.11519 · 2019 · Cited by 10

Computer VisionEmbedded Systems and Computer ArchitectureHardware Acceleration and Co-design

Abstract

Making a single network effectively address diverse contexts---learning the variations within a dataset or multiple datasets---is an intriguing step towards achieving generalized intelligence. Existing approaches of deepening, widening, and assembling networks are not cost effective in general. In view of this, networks which can allocate resources according to the context of the input and regulate flow of information across the network are effective. In this paper, we present Context-Aware Multipath Network (CAMNet), a multi-path neural network with data-dependant routing between parallel tensors. We show that our model performs as a generalized model capturing variations in individual datasets and multiple different datasets, both simultaneously and sequentially. CAMNet surpasses the performance of classification and pixel-labeling tasks in comparison with the equivalent single-path, multi-path, and deeper single-path networks, considering datasets individually, sequentially, and in combination. The data-dependent routing between tensors in CAMNet enables the model to control the flow of information end-to-end, deciding which resources to be common or domain-specific.

SMPTE ST 2110 compliant scalable architecture on FPGA for end to end uncompressed professional video transport over IP networks

Nipuna Ranasinghe, Ravindu Bangamuarachchi, Jayath Seneviratne, Achini Jayawardane, Ajith Pasqual, RMAU Senarath

Conference ASAP 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP) , vol. 2160 , pp. 235-238 · 2019 · Cited by 7

FPGA and Reconfigurable ComputingHardware Acceleration and Co-design

Abstract

SMTPE ST 2110 is a professional video over IP standard which enables uncompressed video to be transported as separate video, audio and ancillary data streams, allowing true flexibility in media workflows. Uncompressed video transmission allows professional video environments to achieve high quality video distribution while meeting strict latency requirements. Although this standard can be implemented on software, hardware solutions can achieve superior performance, lower latency and lower power consumption while efficiently handling jitter and packet bursts. This paper presents an FPGA based hardware implementation of a SMPTE ST 2110 compliant end to end solution supporting uncompressed video resolutions of up to 4K at 30fps. Due to its scalability, the architecture can be easily extended to support higher video resolutions and/or multiple video streams. Additionally, the interface modularity of the …

Hardware and software co-design for object detection with modified vibe algorithm and particle filtering based object tracking

Yasitha M Wijesinghe, Jayathu Samarawickrama, Dileeka Dias

Conference ICIIS 2019 14th Conference on Industrial and Information Systems (ICIIS) , pp. 506-511 · 2019 · Cited by 5

Computer VisionEmbedded Systems and Computer ArchitectureHardware Acceleration and Co-design

Abstract

This paper describes a hardware and software codesign approach for object detection and tracking algorithm which is based on modified ViBe background subtraction method and scale adaptable particle filtering algorithm. The modified ViBe performs with a close accuracy to the original work of ViBe but with less complexity and it outperforms the Mixture of Gaussian(MoG) method. Since the modified algorithm has a low off chip memory access requirement, the real time object detection in embedded level with the help of hardware acceleration techniques could be achieved. The implemented particle filtering algorithm is capable of adapting to the scale variation of the tracking objects. After careful investigation of the time consumption profile of each function in our algorithm, the complete algorithm was implemented in IoT edge devices targeted Avnet Ultra 96 development board which is based on Xilinx Zynq …

FPGA IP for real-time 4K HDR image decoding in VR devices

Kamalakkannan Kamalavasan, Ratnasegar Natheesan, Kathirgamaraja Pradeep, Sivakumaran Gowthaman, Sivakaneshan Aravinth, Ajith Pasqual

Conference LASCAS 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) , pp. 101-104 · 2019 · Cited by 3

FPGA and Reconfigurable ComputingHardware Acceleration and Co-design

Abstract

Quad High Definition (QHD/4K) Virtual Reality (VR) Headsets with High Dynamic Range (HDR) technology will provide a superior experience to users. Wireless VR headsets are attractive as it offers freedom on mobility and higher user comfort. Cloud and workstations are capable of rendering 4K HDR scenes in real-time with ease. The efficient transmission of these scenes through wireless network requires the use of compression techniques. Decoding 4K HDR frames at VR devices in real-time is a challenge. Given the power and memory efficiency of the hardware decoders, in this paper we propose JPEG-XT Profile C based hardware architecture to decode 4K HDR frames in real-time. We employ novel methods for merged base and residual layer decoding pipelines, design of probability-based hybrid Huffman lookup table architecture and sparsity aware inverse zig-zag processing. Our decoder is implemented …