Department Publications

Higher compression efficiency in HEVC encoders comes with increased computational complexity, making real time encoding of high resolution videos a challenging task. This challenge can be addressed by software, yet hardware solutions are more appealing due to their superior performance and low power consumption. This paper presents an FPGA based hardware implementation of an all intra HEVC encoder, which can encode 8 bits per sample, 1920×1080 resolution, 30 frames per second raw video, that is viable in real time even at low operating frequencies. A major obstacle to real time encoding in available architectures is the dependency created by reference generation. Moreover, each coding unit (CU) has to be processed in multiple configurations to determine the most efficient split and prediction mode representation, based on the bit stream generated. We propose a new three stage architecture to …

Increasing demands for faster, more responsive and manageable networks have brought about a different approach to networking - Software Defined Networking (SDN). SDN introduces flow-based networking with a centralized controller. Matching incoming traffic flows with rules sent by the controller is an integral part of traffic forwarding in SDN. How efficiently this is carried out has a huge impact on network performance. In this paper, we present a high-performance, low-cost architecture for flow matching in an SDN switch. Our architecture consists of a dedicated unit for flow matching and a custom processor. Novel design of the flow match unit reduces matching latency significantly, when compared with the generic architecture, while also reducing usage of costly resources like TCAMs. When testing on FPGA platforms, implementing the system required only a minimum amount (around 10% on Virtex-7) of …