Sunanda Gamage, Ajith Pasqual
Conference
ICON 2012 18th IEEE International Conference on Networks (ICON) , pp. 52-57 · 2012 · Cited by 18
Network Optimization and IntelligenceHardware Acceleration and Co-design
Abstract
Packet Classification is the enabling function for many Internet functions like QoS and Security. In this paper we propose a Classification engine architecture which exploits parallelism to increase throughput. The architecture also make use of the Temporal locality observed in Internet traffic positively by employing Popular Rule Caching mechanism to increase the classification throughput. We also introduce Rule Splitting mechanism to increase the accuracy of the rule caching mechanism. Simulation results revealed that the architecture is capable of achieving a throughput of more than 200Gbps when lowest amount of temporal locality is present for worst case packet size of 40 bytes.
Thusitha N Chandrapala, LMAP Cabral, Sapumal Ahangama, Thilina S. Ambagahawaththa, Jayathu Samarawickrama
Conference
FPL 22nd International Conference on Field Programmable Logic and Applications (FPL) , pp. 243-248 · 2012 · Cited by 1
Computer VisionFPGA and Reconfigurable ComputingHardware Acceleration and Co-design
Abstract
Motion Blur due to the relative motion between the camera and object can seriously degrade image quality. We present an FPGA based motion blur detection and correction algorithm which is implemented on top of a configurable soft-processor based architecture. The system consists of two main modules. The blur detection module identifies the blur length and angle, and the restoration module uses regularized inverse filtering to remove the motion blur. The Processing algorithms are implemented as separate cores on the FPGA fabric where the soft processor core is only used for managing system configuration. The system can achieve a frame rate of 15fps for a 720p HD video stream.
