4 publications found
Naduni Damsari Liyanage, Chamith Wijenayake, Chamira U. S. Edussooriya, Arjuna Madanayake, Panajotis Agathoklis, Leonard T Bruton, Eliathamby Ambikairajah
Journal
Signal Processing , vol. 167 , pp. 107294 · 2020 · Cited by 25
Computer VisionDigital Signal ProcessingFPGA and Reconfigurable Computing
Abstract
Low-complexity signal processing algorithms and reconfigurable digital hardware architectures are proposed for multi-depth filtering and occlusion suppression in 4-D light fields (LFs). The proposed multi-depth-pass (MDP) and multi-depth-reject (MDR) 4-D filters allow simultaneous enhancement of planar objects at multiple desired depths and attenuation of planar objects at multiple undesired depths, thereby achieving electronically tunable multi-depth focusing. Partial-separability and recursive nature of the proposed MDP and MDR transfer functions ensure ultra-low hardware complexity suitable for real-time processing of large volume of input samples encountered in 4-D LFs. Filter synthesis details and examples with synthetic and real LFs of size 15 × 15 × 434 × 625 are presented. A generic framework encapsulating a multitude of possible digital hardware realizations is described, employing J …
Sravan Kumar Pulipati, Viduneth Ariyarathna, Ashira L Jayaweera, Chamira U. S. Edussooriya, Chamith Wijenayake, Leonid Belostotski, Arjuna Madanayake
Conference
IMS 2020 IEEE/MTT-S International Microwave Symposium (IMS) , pp. 1077-1080 · 2020 · Cited by 15
Array and Radar Signal ProcessingFPGA and Reconfigurable ComputingAntennas and Electromagnetic Propagation
Abstract
This paper describes a technique for de-embedding electromagnetic mutual coupling effects between nearest neighbors of a ULA receiver. Measured S-parameters across a range of frequencies of interest are used in a closed-form mathematical model that relates measured S-parameters, measured LNA reflection coefficients, and transmission line parameters to digital beamformer design equations, such that the beam shape distortions arising from mutual coupling can be compensated in the DSP algorithm. A 5.8 GHz 32-element receiver array with custom receivers and 32-channel Xilinx Virtex-6 Sx35 FPGA based DSP system implementing a real-time complex-valued Frost beamformer operating at IF is proposed to show the benefits of de-embedding mutual coupling for far-field side-lobe suppression. The worst-case side-lobe level is reduced by 11.2 dB, and the average side-lobe level is reduced by 5.2 dB, for …
Naduni Damsari Liyanage, Chamith Wijenayake, Chamira U. S. Edussooriya, Arjuna Madanayake, Renato J Cintra, Eliathamby Ambikairajah
Conference
ISCAS 2020 IEEE international symposium on circuits and systems (ISCAS) , pp. 1-5 · 2020 · Cited by 8
Computer VisionDigital Signal ProcessingFPGA and Reconfigurable Computing
Abstract
A low-complexity codec and a hardware architecture are proposed for achieving real-time compression of four-dimensional (4-D) light field (LF) signals captured from camera/lenslet arrays. The proposed system employs the 4-D extension of the two-dimensional (2-D) 8×8 approximate discrete cosine transform (ADCT) that has recently appeared in the literature. Motivated by the partial separability of the multidimensional spectrum of LFs, the proposed 4-D ADCT is obtained by cascading 2-D inter-view and 2-D intra-view transform stages. Software simulations are provided to confirm the performance of the 4-D ADCT based compression and comparisons are made with respect to 2-D inter-view only and 2-D intra-view only ADCT-based compression. Proposed digital architectures are validated using stepped hardware co-simulation on a Xilinx Virtex-7 VC-707 FPGA platform verifying 597 MHz maximum possible …
Low Power FPGA-based Hardware Accelerator for Autonomous Navigation of Mobile Robots
Senthurbavan Kirubaharan, Peshala Jayasekara, Dilan Weerakkody
Conference
ACRA Australasian Conference on Robotics and Automation (ACRA) · 2020 · Cited by 1
Mobile Robotics and NavigationFPGA and Reconfigurable ComputingHardware Acceleration and Co-design