Department Publications

This paper presents the design, implementation, and the experimental verifications of a 2.4-GHz multibeam array receiver based on two-dimensional (2-D) spatially bandpass (SBP) digital plane wave (PW) filters. The digital array receiver consists of 2.4-GHz 16-element uniform linear array, and quadrature sampling is employed to process the broadband PWs at the baseband. Both 2-D finite impulse response (FIR) and infinite impulse response (IIR) digital filters having multiple trapezoidal-shaped passbands are employed as the 2-D SBP digital PW filters. Both 2-D FIR and IIR trapezoidal filters are implemented on a Xilinx Virtex 6 sx475t field programmable gate array chip that comes with the reconfigurable open architecture computing hardware version-2 (ROACH-2) platform. The 16 in-phase and quadrature-phase downconverted signals are sampled using the ROACH-2 platform and are processed using the …

In Electroencephalography (EEG) classifiers, processing of EEG signals consists of extracting features from EEG signal and then processing those features to classify the signals. As of today, in most EEG processing systems, the classification part is done on software platform even though the feature extraction is done on hardware. Hence this require an operating system which limits the development of portable medical devices. This paper presents the design and implementation of feature classification in EEG signal processing system on Field Programmable Gate Array (FPGA) hardware platform. The classification is done with two-class Linear Discriminant Analysis (LDA), based on the features extracted using Discrete Wavelet Transform (DWT), for EEG signals obtained through PhysioNet website. The final design has minimum resource utilization, hence is able to implement on Basys 3 Artix-7 FPGA Board …

Due to the increasing heterogeneity in network user requirements, dynamically varying day to day network traffic patterns and delay in-network service deployment, there is a huge demand for scalability and flexibility in modern networking infrastructure, which in return has paved way for the introduction of Software Defined Networking (SDN) in core networks. In this paper, we present an FPGA-based switch that is fully compliant with OpenFlow; the pioneering protocol for southbound interface of SDN. The switch architecture is completely implemented on hardware. The design consists of an OpenFlow Southbound agent which can process OpenFlow packets at a rate of 10Gbps. The proposed architecture speed scales up to 400Gbps while it consumes only 60% of resources on a Xilinx Virtex-7 featuring XC7VX485T FPGA.

SMTPE ST 2110 is a professional video over IP standard which enables uncompressed video to be transported as separate video, audio and ancillary data streams, allowing true flexibility in media workflows. Uncompressed video transmission allows professional video environments to achieve high quality video distribution while meeting strict latency requirements. Although this standard can be implemented on software, hardware solutions can achieve superior performance, lower latency and lower power consumption while efficiently handling jitter and packet bursts. This paper presents an FPGA based hardware implementation of a SMPTE ST 2110 compliant end to end solution supporting uncompressed video resolutions of up to 4K at 30fps. Due to its scalability, the architecture can be easily extended to support higher video resolutions and/or multiple video streams. Additionally, the interface modularity of the …

A real-time directional sensing system is proposed for 2.4 GHz ISM band by exploiting the concept of spatiotemporal spectral white spaces. The proposed system consists of a 16-element patch antenna array, an FFT-based multi-beam beamformer and an energy detector. Our system operates at the baseband with quadrature sampling. Furthermore, digital architectures for two energy detectors that employ integrate-and-dump circuits are presented. With the multi-beam beamformer, the first energy detector can be employed to directional sensing and the second can be employed for both directional and spectral sensing of radio frequency sources. The multi-beam beamformer having 16 beams and the energy detectors are implemented on a ROACH-2 based FPGA system with a 160 MHz clock. With an 8-point temporal FFT, the second energy detector provides approximately 20 MHz bandwidth per temporal FFTbin …

Quad High Definition (QHD/4K) Virtual Reality (VR) Headsets with High Dynamic Range (HDR) technology will provide a superior experience to users. Wireless VR headsets are attractive as it offers freedom on mobility and higher user comfort. Cloud and workstations are capable of rendering 4K HDR scenes in real-time with ease. The efficient transmission of these scenes through wireless network requires the use of compression techniques. Decoding 4K HDR frames at VR devices in real-time is a challenge. Given the power and memory efficiency of the hardware decoders, in this paper we propose JPEG-XT Profile C based hardware architecture to decode 4K HDR frames in real-time. We employ novel methods for merged base and residual layer decoding pipelines, design of probability-based hybrid Huffman lookup table architecture and sparsity aware inverse zig-zag processing. Our decoder is implemented …