Department Publications

In recent years, Convolution Neural Network (CNN) gained great success in many applications, especially in computer vision. Now adapting CNN inference on edge devices has become an active research area in embedded vision and hot topic in Edge AI. The primary design hurdles for implementing CNN inference on embedded systems are limited computational resource, memory resource, and power budget. This study presents a novel architecture for SqueezeNet [1] like CNN models, which can be extended to support any CNN model as well. We address two approaches to mitigate resource constraints. First, we use a custom floating point(12 bit for computation and 8bit for storing). Second is slicing the model into a repetitive block called computation blocks. Computation block can be configured dynamically by the host processor to operate in a different mode. We have implemented SqueezeNet v1.1 for …

The design and hardware implementation of a low-complexity signal processing algorithm is proposed for real-time depth-velocity filtering in 5-D light field videos (LFVs). The proposed design is based on a stable 5-D infinite impulse response digital filter having three cascaded sections, each synthesized using the concept of multidimensional passive network resonance. A novel semi-systolic hardware implementation is proposed. Each section of the filter is implemented and tested on a Xilinx Virtex-7 FPGA platform using MATLAB-based hardware co-simulation with both synthetic and real LFV signals. A real-time processing throughput of 467 LFV frames/s is implied with each section of the filter operating at 204, 164, and 115 MHz for input LFV frames of size 9 × 9 × 220 × 360.

This paper presents the implementation of a two-dimensional (2-D) finite-impulse-response (FIR) trapezoidal filter based beamforming array receiver. A 2.4 GHz 16-element receive-mode IQ array is designed and used for physically measuring the beam patterns corresponding to 2-D FIR trapezoidal filters. The 16-element beamformer is implemented using the reconfigurable open architecture computing hardware version-2 (ROACH-2) field programmable gate array (FPGA) platform to perform analog to digital conversion and digital signal processing. The 2-D FIR trapezoidal filter is designed as a 16-spatial input 32-tap filter and is implemented targeting the ROACH-2’s Xilinx Virtex 6 (sx475t) FPGA chip as a filter-and-sum architecture. The receiver array is precisely rotated (keeping the transmitter fixed) to digitally measure the received energy by integrating the instantaneous power of the output of the 2-D FIR …

Convolutional Neural Networks (CNNs) are widely used in deep learning applications, e.g. visual systems, robotics etc. However, existing software solutions are not efficient. Therefore, many hardware accelerators have been proposed optimizing performance, power and resource utilization of the implementation. Amongst existing solutions, Field Programmable Gate Array (FPGA) based architecture provides better cost-energy-performance trade-offs as well as scalability and minimizing development time. In this paper, we present a model-independent reconfigurable co-processing architecture to accelerate CNNs. Our architecture consists of parallel Multiply and Accumulate (MAC) units with caching techniques and interconnection networks to exploit maximum data parallelism. In contrast to existing solutions, we introduce limited precision 32 bit Q-format fixed point quantization for arithmetic representations and …