Department Publications

With the popularization of a quad high-definition/4K video being dependent on the availability of real-time High Efficiency Video Coding (HEVC) decoders, hardware implementations have become more appealing due to their superior performance and low power consumption. In this paper, a field-programmable gate array (FPGA)-based hardware implementation of a 4K 30 frames/s real-time HEVC decoder is presented. An elastically pipelined decoder architecture is used to absorb variations in processing time and each pipeline stage is optimized to use available FPGA primitives. FPGA-specific challenges in managing critical path delays to achieve a target operating frequency of 150 MHz required many architectural novelties, such as exploitation of the sparsity of transformed coefficient matrix, single-cycle reference pixel processing in intra prediction, and flexible block ordering in deblocking filter/sample …

This paper presents an implementation technique for the 40Gbps Ethernet Physical Coding Sublayer (PCS). The functionality of the 40Gbps Ethernet PCS is specified in the IEEE 802.3ba standard's clause 82. The paper also presents a scheme of verification of this implementation using an FPGA setup.