Udara Piumal De Silva, Anusha Lokumarambage, Hasantha Malavipathirana, Chathuranga Mohottala, Subramaniam Thayaparan
Conference
ISCAIE 2016 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE) , pp. 21-25 · 2016 · Cited by 4
Digital Electronic SystemsVLSI and ASIC Design
Abstract
This paper identifies the challenges involved in designing the 100 Gigabit per second (Gbps) Ethernet Physical Coding Sublayer (PCS) Semiconductor Intellectual property (IP) compliant with IEEE 802.3 standard. Challenges are discussed under the two topics, implementation challenges and verification challenges. Furthermore, our solutions to identified challenges are presented in the paper.
Anuradha Nanayakkara, Subramaniam Thayaparan
Conference
ICOIN 2016 International Conference on Information Networking (ICOIN) , pp. 151-154 · 2016 · Cited by 1
Digital Electronic SystemsVLSI and ASIC Design
Abstract
This paper analyses the receiver of 40GBASE PCS Sub layer specified by IEEE 802.3ba CSMA/CD standards. Based on the analysis, possible optimization parameters for the receiver FIFO are identified. Proper functionality of the proposed design is verified with simulation results. The optimization of receiver FIFO design may lead to reduce the gate count, area and power consumption in ASIC design.
