Department Publications

This paper presents the implementation and analysis of a low complex architecture for a fast locking Phase Locked Loop. In this paper, we analyse a high speed mixed signal PLL architecture and its components such as phase frequency detector, charge pump, voltage controlled oscillator etc. are further reviewed. The simulation results show that proposed PLL design achieves locking within 1 μβ and it operates at 5 GHz featuring a significant P k -P k jitter value less than 10 ps and root-mean-square jitter less than 5 ps. Mathematical modeling and simulations of the proposed PLL architecture are also presented.